Computer systems are being required to achieve higher processing speeds and larger processing volume (throughput). This increases the importance of distributed processing, which can be realized by using plural processors. In order to meet the requirements of both higher processing speed and larger processing volume at adequate cost, distributed processing has to be realized at a high efficiency. Barrier synchronization is one technique that can realize distributed processing at a high efficiency, and is widely used for high-performance computer systems nowadays.
To perform barrier synchronization, plural processors are divided into synchronization groups so that the progress of processes is managed in units of synchronization groups. Under management using this method, the execution target is shifted from a currently executed process to the next process when all processors belonging to a synchronization group have finished the process that they are currently executing. Barrier synchronization devices for realizing barrier synchronization are disclosed, for example, by Patent Documents 1 through 3.
In order to manage the progress of processes in units of synchronization groups, each processor has to report the execution status of a process to other processors, and when each processor has entered a situation in which it has to shift to the next process, the processor also has to report this fact to other processors. Accordingly, distributed processing is roughly classified into two portions; a parallel processing portion and a coordinated operation portion. A parallel processing portion executes process that respective processors have to execute parallelly. A coordinated operation portion is executed in order to make processors operate in a coordinated manner. In order to increase efficiency in distributed processing, it is important to minimize the ratio (time period) needed to execute a coordinated operation portion (synchronization process).
In recent years, improvement in semiconductor technology has promoted commercialization of multi-core processor having plural processor cores (each processor core having various units for decoding and executing instructions, a registers, cache memory, and the like) each having a computing function. In this type of multi-core processor, synchronization groups are assigned to individual processor cores. This assignment can bring about a situation in which all processor cores belonging to the same synchronization group are in one multi-core processor. It is thought to be important to take this situation into consideration when a time period taken to execute a coordinated operation portion is to be reduced.
Improvement in semiconductor technique has contributed to an increase in processing speed and circuit density of processors and to an increase in capacity of memory. As a result, higher computation performance is realized using an area smaller than realized by conventional techniques, and such areas have become larger. However, the speed of accessing main memory is still lower than the processing speed of a processor. Rather, the gap between processing the speed of processors and operation speed of main memory has become more serious. Accordingly, when some information is transferred via main memory, a period of time taken to execute a coordinated operation portion is influenced by the operation speed of the main memory, which is lower. This point as well has to be taken into consideration in reducing a period of time taken to execute a coordinated operation portion.
Patent Document 1: Japanese Laid-open Patent Publication No. 6-187303
Patent Document 2: Japanese Laid-open Patent Publication No. 9-6734
Patent Document 3: Japanese Laid-open Patent Publication No. 2005-71109